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RM0008
Universal serial bus full-speed device interface (USB)
Figure 190. USB peripheral block diagram
DP
Analog
DM
USB clock (48 MHz)
USB
transceiver
PCLK1
Suspend
timer
RX-TX
Control
S.I.E.
Clock
recovery
Endpoint
selection
Control
registers & logic
Interrupt
registers & logic
Packet
buffer
interface
Endpoint
registers
Endpoint
registers
Arbiter
Packet
buffer
memory
Register
mapper
Interrupt
mapper
APB1 wrapper
APB1 interface
PCLK1
APB1 bus
IRQs to NVIC
The USB peripheral provides an USB compliant connection between the host PC and the
function implemented by the microcontroller. Data transfer between the host PC and the
system memory occurs through a dedicated packet buffer memory accessed directly by the
USB peripheral. The size of this dedicated buffer memory must be according to the number
of endpoints used and the maximum packet size. This dedicated memory is sized to 512
bytes and up to 16 mono-directional or 8 bidirectional endpoints can be used.The USB
peripheral interfaces with the USB host, detecting token packets, handling data
transmission/reception, and processing handshake packets as required by the USB
standard. Transaction formatting is performed by the hardware, including CRC generation
and checking.
Each endpoint is associated with a buffer description block indicating where the endpoint
related memory area is located, how large it is or how many bytes must be transmitted.
When a token for a valid function/endpoint pair is recognized by the USB peripheral, the
related data transfer (if required and if the endpoint is configured) takes place. The data
buffered by the USB peripheral is loaded in an internal 16 bit register and memory access to
the dedicated buffer is performed. When all the data has been transferred, if needed, the
Doc ID 13902 Rev 9
513/995
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